Reference current generator is applied in integrated circuits for supplying reference currents to analog circuits. FIG. 1 shows a circuit diagram of a conventional reference current generator 10, which comprises a resistor Rptat having a resistance proportional to the absolute temperature for a current Iptat1 to flow therethrough to produce a voltage drop ΔV thereacross, a current mirror 12 including a referent branch consisting of an NMOS transistor T4 to couple with the current Iptat1 and a mirror branch consisting of an NMOS transistor T3 for generating a current Iptat2 by mirroring the current Iptat1, a PMOS transistor T1 coupled between a supply voltage VDD and the transistor T3 and having its gate and drain coupled together, a PMOS transistor T2 coupled between the NMOS transistor T4 and the resistor Rptat and having its gate coupled to the gate of the PMOS T1, and an NMOS transistor T5 having its gate coupled to the gate of the NMOS transistor T4 for generating a current Idc_ld1 proportional to the current Iptat1 to supply for a load 14 coupled between the supply voltage VDD and the NMOS transistor T5. The PMOS transistors T1 and T2 have a size ratio 1:α, and the NMOS transistors T3, T4 and T5 have a size ratio β:1:γ. When the reference current generator 10 operates, a voltage drop VG is resulted between the source and drain of the PMOS transistor T1, the voltage drop ΔV is resulted across the resistor Rptat, the current Iptat1 flows from the PMOS transistor T2 to the NMOS transistor T4, and the current Iptat2 flows from the PMOS transistor T1 to the NMOS transistor T3.
FIG. 2 shows another conventional reference current generator 20, which has a structure similar to that of the reference current generator 10 of FIG. 1, but uses a PMOS transistor T5 connected between the supply voltage VDD and the load 14 instead, such that the current Idc_ld2 is produced to supply for the load 14. Additionally, the size ratio of the PMOS transistors T1, T2 and T5 is 1:α:γ, and the size ratio of the NMOS transistors T3 and T4 is β:1.
Referring to FIG. 1 and FIG. 2, due to the size ratio between the NMOS transistors T3 and T4, the currents Iptat1 and Iptat2 are determined byIptat2=β×Iptat1.  [EQ-1]On the other hand, the currents Iptat1 and Iptat2 can be determined by
                                          Iptat            ⁢                                                  ⁢            1                    =                      α            ×                          I              D0                        ×                          ⅇ                              (                                  VG                                      n                    ×                    Vt                                                  )                                      ×                          ⅇ                              (                                  ÷                                                            Δ                      ⁢                                                                                          ⁢                      V                                        Vt                                                  )                                                    ,                                  ⁢        and                            [                  EQ          ⁢                      -                    ⁢          2                ]                                                      Iptat            ⁢                                                  ⁢            2                    =                                    I              D0                        ×                          ⅇ                              (                                  VG                                      n                    ×                    Vt                                                  )                                                    ,                            [                  EQ          ⁢                      -                    ⁢          3                ]            where Vt is the thermal voltage. Substituting the equations EQ-2 and EQ-3 to the equation EQ-1, it is obtained
                              α          ×          β                =                              e                                          Δ                ⁢                                                                  ⁢                V                            Vt                                .                                    [                  EQ          ⁢                      -                    ⁢          4                ]            Further, the voltage drop ΔV across the resistor Rptat can be calculated byΔV=Iptat1×Rptat.  [EQ-5]Therefore, based on the equation EQ-4, the equation EQ-5 can be rewritten as
                              Iptat          ⁢                                          ⁢          1                =                              Vt            Rptat                    ×                                    ln              ⁡                              (                                  α                  ×                  β                                )                                      .                                              [                  EQ          ⁢                      -                    ⁢          6                ]            From the equation EQ-6, it is shown that the greater the resistance Rptat is, the less the current Iptat1 is, and hence, in order to reduce the power consumption by reducing the current Iptat1, the resistance Rptat must be increased. However, the occupying area of the resistor Rptat on a chip is also enlarged when the resistance Rptat is increased, and therefore the reference current generator 10 or 20 will have a larger chip size. Thereby, it is desired a reference current generator that has reduced chip size and less power consumption.